A. Field of the Invention
The present invention relates generally to monitoring systems and, more particularly, to systems and methods for monitoring and verifying integrated circuit internal states.
B. Description of Related Art
Conventional Integrated Circuit (IC) fabrication processes generally involve some level of error that can lead to defective or wholly inoperative fabricated ICs. Therefore, for the purpose of quality control, techniques have been developed for testing ICs post-fabrication. Such techniques have conventionally involved testing at the register transfer level (RTL). Testing at the RTL level has typically been implemented by specifying a path to the internal signals from the top-level of the design through the design hierarchy. This approach, however, is impractical for testing the IC at the gate-level since the design hierarchy and the signal names are usually non-obvious or non-present at the gate-level. Thus, register transfer level testing techniques are not easily applicable to gate-level testing.
Therefore, there exists a need for systems and methods that can test and verify IC internal states without requiring knowledge of the IC register transfer level hierarchy.